The wavelength of a millimeter wave varies from 10 millimeters to 1 millimeter and the frequency in use may range from 30 GHz to 300 GHz. The characteristics of the millimeter waves, such as anti-interference and anti-interception, make millimeter waves preferable for high data-rate wireless communication. In the millimeter wave communication system, a phase locked loop is an important component, which generates a stable signal at for frequency conversions. By comparing the phase of the signal generated by PLL its own with the phase of another signal from an external source at low frequency, a PLL can adjust the output signal and provide a carrier with high purity at high frequency range.
With reference to FIG. 1, a conventional PLL comprises a phase-frequency detector (PFD) (10), a charge pump (11), a loop filter (12), a voltage controlled oscillator (VCO) (13) and a frequency divider (14).
The PFD (10) detects the phase difference between a reference signal (15) and a feedback signal (16).
The charge pump (11) is connected to the PFD (10) and generates a control voltage (17) based on the phase difference between the reference signal (15) and the feedback signal (16).
The loop filter is a low-pass filter that filters out high frequency components of the control voltage (17), which is connected to the charge pump (11).
The VCO (13) generates an oscillating signal (18) based on the control voltage (17).
The frequency divider (14) divides frequency of the oscillating signal (18) into the frequency that the reference signal (15) oscillates at. The divided signal at the output of the frequency divider is the feedback signal (16). The feedback signal (16) is further input to the PFD (10).
Since the oscillation frequency for millimeter wave applications is higher than 30 GHz and the frequency of the reference signal (15) is 200 MHz generated by a crystal oscillator, the division ratio is more than 150.
It is known that the phase noise within the loop bandwidth is dominated by the reference signal (15) and increasing the loop bandwidth can suppress the phase noise contributed by VCO (13). However, if the loop bandwidth is close to the frequency of reference signal, reference spurs may appear in each side band of the desired signal at the output of the PLL with an offset value of the reference frequency. As a rule-of-thumb, the loop bandwidth of a PLL is generally designed around 1/10 frequency of reference signal (15). Therefore in theory, the higher the frequency of the reference signal is, the wider loop bandwidth and the better phase noise of the PLL will be. Unfortunately, there is another constraint to the loop bandwidth of a PLL, which is the upper limit of the operation frequency of the PFD.
A conventional tri-state PFD (2) comprises an AND logic gate (21) and two D Flip-Flops (DFF) (20) as is shown in FIG. 2.
The DFFs (20) respectively receive a reference signal (25) and a feedback signal (26).
The AND logic gate (21) is connected to the DFFs (20). When the phases of the reference signal (25) and the feedback signal (26) are matched (synchronized), the AND logic gate (21) will reset the DFFs (20).
A drawback of such conventional tri-state PFD (2) is its operating frequency limited by the DFFs (20). If the frequencies of the reference signal (25) and the feedback signal (26) are higher than the operating frequency of the DFFs (20), unpredictable errors may occur, which limits the frequency of reference signal as well as the operation frequency of the PFD.
Another kind of conventional PFD (3) is proposed to resolve the issue of conventional tri-state PFD (2) as shown in FIG. 3, which comprises only one D Flip-Flop (DFF) (31) and no reset path. The DFF (31) of this PFD (3) is used to delay the phase of a reference signal (32) by 90 degrees. Nevertheless, the dependence on such 90 degree phase delay makes the design of DFF more complicated when the frequency of reference signal is increased, which also constrains operation frequency of PFD.
To resolve the issues about the limited loop bandwidth of conventional PFDs, a PFD capable to handle high frequency reference signal is proposed, which can provide the PLL with a wider loop bandwidth and a better out-band noise suppression.